Synopsys Announces That Micron Technology, Inc., Selects Its SiVL DFM Solution for 90-nanometer Production

MOUNTAIN VIEW, Calif., Nov. 16 /PRNewswire-FirstCall/ -- Synopsys, Inc. (NASDAQ: SNPS), the world leader in semiconductor design software, today announced that Micron Technology, Inc., a leading provider of semiconductor products and memory modules, has chosen Synopsys' SiVL(R) silicon-versus-layout software to help implement its advanced DRAMs, flash memories, CMOS image sensors, and other semiconductor components. Micron selected the SiVL software, a key component of Synopsys' comprehensive DFM solution that addresses manufacturability and yield issues of complex integrated circuit (IC) designs, because of its ability to catch critical lithography errors prior to tapeout improving manufacturing efficiency at advanced technology nodes such as 90-nm and below.

"At sub-wavelength geometries, it is necessary to verify that each design prints as expected before it goes through fracturing, mask manufacturing, and wafer production," said Eugene Delarosa, Micron's advanced mask development manager. "Using the SiVL software before mask manufacturing allows us to quickly find and address layout anomalies thereby providing us with an opportunity to achieve our aggressive production schedules."

As process geometries continue to shrink to 90-nm and below, the use of reticle enhancement techniques (RET) increases mask complexity and the chance that lithography errors will occur. Finding these errors requires accurate, full-chip simulation and extensive coverage. The SiVL tool's unique 'check-figure' capability identifies the critical features most likely to have errors and then applies simulation-based lithography rule checks (LRC) to find them. It also performs pattern-based checks, such as mask rule checks (MRC), to improve mask manufacturability. The SiVL tool achieves fast turnaround time through its unique distributed processing capability that has been proven scalable on standard, widely available low cost compute platforms.

"The rapidly expanding use of RET in the 90 and 65 nanometer nodes dramatically increases the chances of killer lithography-related defects going undetected. The SiVL software helps finds these defects thereby preventing costly time-to-market delays and enabling RET closure," said Tom Kingsley, product marketing manager for lithography verification at Synopsys. "The importance of verifying that a chip will print to silicon correctly is one more way Synopsys DFM solutions help customers achieve manufacturable designs and accelerate their time to yield."

About Synopsys DFM

Synopsys offers the industry's most comprehensive RTL-to-Silicon solution. Its DFM product family addresses critical yield and manufacturability issues with software products such as the Proteus mask synthesis, CATS(R) mask data preparation, SiVL lithography verification, i-Virtual Stepper(TM) mask defect dispositioning and Taurus(TM) TCAD products. Synopsys leverages this expertise throughout its industry-leading Galaxy(TM) design platform implementation solution in order to help ensure that designs at 90nm and smaller geometries will meet key manufacturing requirements. Synopsys' DFM product family is the solution-of-choice for 130nm yield sensitive, high-value chips, worldwide. 80 percent of all sub-180nm microprocessors, 50 percent of all sub-180nm DRAMs, 80 percent of all sub-180nm FPGA and graphics chips, 75 percent of all sub-180nm cellular baseband chips produced use Proteus, and more than 80 percent of all photomasks produced use CATS.

About Synopsys

Synopsys, Inc. is the world leader in electronic design automation (EDA) software for semiconductor design. The company delivers technology-leading semiconductor design and verification platforms and IC manufacturing software products to the global electronics market, enabling the development and production of complex systems-on-chips (SoCs). Synopsys also provides intellectual property and design services to simplify the design process and accelerate time-to-market for its customers. Synopsys is headquartered in Mountain View, California and has offices in more than 60 locations throughout North America, Europe, Japan and Asia. Visit Synopsys online at http://www.synopsys.com/ .

NOTE: Synopsys, CATS and SiVL are registered trademarks of Synopsys, Inc. iVirtual Stepper and Taurus are trademarks of Synopsys. Micron is a registered trademark of Micron Technology, Inc. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.

CONTACT: Jennifer Scher of Synopsys, Inc., +1-650-584-5594, or
scher@synopsys.com; or Sarah Seifert of Edelman, +1-650-429-2776, or
sarah.seifert@edelman.com, for Synopsys, Inc.

Web site: http://www.synopsys.com/